SY100S307 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – QUINT EXCLUSIVE OR/NOR GATE

QUINT EXCLUSIVE
OR/NOR GATE
SY100S307
FEATURES
DESCRIPTION
s Max. propagation delay of 1000ps
s IEE min. of –58mA
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for improved
noise immunity
s Internal 75KΩ input pull-down resistors
s 50% faster than Fairchild 300K at lower power
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
The SY100S307 is an ultra-fast quint exclusive-OR/
NOR gate designed for use in high-performance ECL
systems. A function output that is the wire-OR result of the
exclusive-OR outputs is also available. The inputs on the
device have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
D1b
D2b
VEE
VEES
D1c
D2c
D2d
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
J28-1
1
16
28
17
27
18
26
19 20 21 22 23 24 25
Oc
Oc
VCCA
VCC
VCC
F
Od
F
D1a
Oa
D2a
Oa
D1b
Ob
D2b
Ob
D1c
Oc
D2c
Oc
24 23 22 21 20 19
D1d
1
18
D2a
D1e
2
17
D1a
D2e
3
Oe 4
Oe 5
Top View 16 Oa
Flatpack
F24-1
15
Oa
14 Ob
Od 6
13 Ob
7 8 9 10 11 12
D1d
Od
D2d
Od
D1e
Oe
D2e
Oe
PIN NAMES
Pin
Dna – Dne
E
Oa – Oe
Oa – Oe
VEES
VCCA
Function
Data Inputs (n-1...5)
Enable Input
Data Outputs
Complementary Data Outputs
VEE Substrate
VCCO for ECL Outputs
Rev.: G Amendment: /0
1
Issue Date: July, 1999