SY100S302 Datasheet, PDF (1/5 Pages) Micrel Semiconductor – QUINT 2-INPUT OR/NOR GATE

QUINT 2-INPUT
OR/NOR GATE
SY100S302
FEATURES
DESCRIPTION
s Max. propagation delay of 700ps
s IEE min. of –45mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for
improved noise immunity
s Internal 75KΩ input pull-down resistors
s 50% faster than Fairchild 300K
s Function and pinout compatible with Fairchild F100K
s Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
The SY100S302 offers five 2-input OR/NOR gates
designed for use in high-performance ECL systems. The
five gates are controlled by a common Enable signal. All
inputs have 75KΩ pull-down resistors and all outputs are
buffered.
PIN CONFIGURATIONS
D1b
D2b
VEE
VEES
E
D1c
D2c
11 10 9 8 7 6 5
12
4
13
3
14
Top View
2
15
PLCC
J28-1
1
16
28
17
27
18
26
19 20 21 22 23 24 25
Oc
Oc
VCCA
VCC
VCC
Od
Od
D1a
Oa
D2a
Oa
D1b
Ob
D2b
Ob
D1c
Oc
D2c
Oc
24 23 22 21 20 19
D1d
1
18
D2a
D2d
2
17
D1a
D1e
3
D2e
4
Oe 5
Top View 16 Oa
Flatpack
F24-1
15
Oa
14 Ob
Oe 6
13 Ob
7 8 9 10 11 12
D1d
Od
D2d
Od
D1e
Oe
PIN NAMES
D2e
Oe
Pin
Function
E
Dna – Dne
Data Inputs (n-1...5)
E
Enable Input
Oa – Oe
Data Outputs
Oa – Oe
Complementary Data Outputs
VEES
VEE Substrate
VCCA
VCCO for ECL Outputs
Rev.: G Amendment: /0
1
Issue Date: July, 1999