SY100EL29V Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 5V/3.3V DUAL DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP w/SET AND RESET

5V/3.3V DUAL DIFFERENTIAL
DATA AND CLOCK
D FLIP-FLOP w/SET AND RESET
ClockWorks™
SY100EL29V
FEATURES
s 3.3V and 5V power supply option
s Differential D, CLK and Q
s Extended V_EE range of –3.0V to –5.5V
s V_BB output for single-ended use
s 1100MHz min. toggle frequency
s Asynchronous Reset and Set
s Fully compatible with Motorola MC100LVEL29 and
MC100EL29
s Available in 20-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
R0 VCC Q0 Q0 S0 S1 VCC Q1 Q1 VEE
20 19 18 17 16 15 14 13 12 11
QQ
R
S
D CLK
QQ
S
R
D CLK
DESCRIPTION
The SY100EL29V is a dual differential register with
differential data (inputs and outputs) and clock. The
registers are triggered by a positive transition of the
positive clock (CLK) input. A HIGH on the Reset (Rx)
asynchronously resets the appropriate register so that
the Q outputs go LOW. A HIGH on the Set (Sx)
asynchronously resets the appropriate register so that
the Q outputs go HIGH. The Set and Reset inputs cannot
both be HIGH simultaneously.
The differential input structures are clamped so that
the inputs of unused registers can be left open without
upsetting the bias network of the devices. The clamping
action will assert the /D and the /CLK sides of the inputs.
The noninverting input will pull down to V_EE and the
inverting input will be biased around V_CC/2. Because of
the edge-triggered flip-flop nature of the devices,
simultaneously opening both the clock and data inputs
will result in an output which reaches an unidentified but
valid state.
The fully differential design of the devices makes them
ideal for very high frequency applications where a
registered data path is necessary.
1 2 3 4 5 6 7 8 9 10
D0 D0 CLK0 CLK0 VBB D1 D1 CLK1 CLK1 R1
SOIC
TOP VIEW
PIN NAMES
Pin
CLK, /CLK
D[0:1], /D[0:1]
Q[0:1], /Q[0:1]
R₀, R₁
S₀, S₁
V_BB
V_CC
V_EE
Function
Differential Clock Inputs
Differential Data Inputs
Differential Data Outputs
Reset Inputs
Set Inputs
V_BB Reference Output
V_CC
V_EE
TRUTH TABLE
R
S
D
L
L
L
L
L
H
H
L
X
L
H
X
H
H
X
NOTE:
Z = LOW-to-HIGH Transition
CLK
Z
Z
X
X
X
Q
L
H
L
H
Undef
/Q
H
L
H
L
Undef
Rev.: B Amendment: /0
1
Issue Date: February 2000