SY100EL16VO Datasheet, PDF (1/6 Pages) Micrel Semiconductor – 3.3V/5V 800MHz PRECISION PECL AMPLIFIER WITH LOW GAIN FEEDBACK

3.3V/5V 800MHz
PRECISION PECL AMPLIFIER
WITH LOW GAIN FEEDBACK
SY100EL16VO
FINAL
FEATURES
s 3.3V and 5V ±10% power supply options
s Guaranteed AC parameters over temperature:
• f_MAX = 800MHz
• < 200ps differential propagation delay (D to Q_FB)
• < 730ps differential propagation delay (D to Q_HG)
• < 250ps t_r / t_f
s Low gain feedback path Q_FB = +10V/V
s Output enable
s V_BB reference output voltage
s Wide temperature range: –40°C to +85°C
s Available in 10-pin (3×3mm) MSOP
DESCRIPTION
The SY100EL16VO is a differential receiver amplifier
optimized for crystal oscillator applications. The device includes
an additional low gain (+10V/V) output stage (Q_FB) ideal for
feedback applications common in crystal oscillator gain blocks.
The SY100EL16VO is fully differential, with a bandwidth
> 800MHz over temperature and voltage. For applications that
require output disable control, an Enable pin (/EN) will force
the differential output into a fixed logic state. The
SY100EL16VO also includes a V_BB reference voltage for
single-ended or AC-coupled applications.
The SY100EL16VO PECL logic is 100k ECL compatible.
Operation is guaranteed over the –40°C to +85°C temperature
range and 3.3V to 5V nominal supply voltage range.
PIN CONFIGURATION
TRUTH TABLE
QFB 1
/QFB 2
D3
/D 4
VBB 5
10 VCC
9 QHG
8 /QHG
7 VEE
6 /EN
/EN
QHG Out
0
Data
1
Logic Low
PIN NAMES
/QHG Out
/Data
Logic High
BLOCK DIAGRAM
Q_FB
/Q_FB
D
/D
V_BB
/EN
LEN Q
LATCH
D
V_CC
Q_HG
/Q_HG
V_EE
Pin
Function
Q_FB, /Q_FB Differential clock outputs for feedback path:
Nominal DC gain +10.
D, /D
PECL, LVPECL, ECL, LVECL differential inputs:
Internal 75kΩ pull-down resistor.
V_BB
V_CC –1.32V reference voltage for single-ended
inputs: It provides the switching reference for the
input differential amplifier. When unused, it can be
left open. For single-ended PECL applications
connect V_BB to /D input, and bypass with a 0.01µF
capacitor to V_CC.
/EN
Enable: PECL compatible input control with internal
75kΩ pull-down resistor. It controls the high-gain
output (Q_HG). When HIGH, Q_HG is low and /Q_HG is
high. /EN is synchronous so that the outputs will only
be enabled/disabled when they are in the LOW state.
V_EE
Negative power supply: For ECL/LVECL operation,
connect to negative supply. For PECL/ LVPECL
operation, connect to GND.
Q_HG, /Q_HG Differential high-gain outputs: Nominal DC gain is
greater than +200.
V_CC
Positive power supply: For ECL/LVECL operation,
connect to V_CC = 0V. For PECL/ LVPECL operation,
connect to either 3.3V or 5.0V. Bypass with 0.1µF//
0.01µF low ESR capacitors.
Rev.: C Amendment: /0
1
Issue Date: February 2003