PL602-35 Datasheet, PDF (1/10 Pages) Micrel Semiconductor – 750kHz – 800MHz Low Phase Noise Multiplier XO

PL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FE AT UR E S
PIN CONFIGURATION
 Selectable 750kHz to 800MHz range.
(Top View)
 Low phase noise output
 -127dBc/Hz for 155.52MHz @ 10kHz offset
 -115dBc/Hz for 622.08MHz @ 10kHz offset
 LVCMOS (PL602-37), LVPECL (PL602-35 and
PL602-38) or LVDS (PL602-39) output.
 12MHz to 25MHz crystal input.
 No external crystal load capacitors required.
 Output Enable selector.
 Selectable /16 to x32 frequency divider/multiplier.
 3.3V operation.
VDD 1
XIN 2
XOUT 3
SEL3^ 4
SEL2^ 5
OE 6
GND 7
1
6
SEL0^
1
5
SEL1^
1
4
GND
1
3
CLKC
1
2
VDD
1
1
CLKT
1
0
GND
 Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GND 8
9 GND
GREEN/RoHS compliant packages.
TSSOP-16L
DESCRIPTION
The PL602-35 (LVPECL with inverted OE), PL602-37
(LVCMOS), PL602-38 (LVPECL), and PL602-39
(LVDS) are high performance and low phase noise XO
IC chips. They provide phase noise performance as
low as –127dBc at 10kHz offset (at 155MHz), by multi-
plying the input crystal frequency up to 32x. The very
low jitter makes them ideal for a wide range of applica-
tions, including SONET/SDH and FEC. They accept
fundamental parallel resonant mode crystals from
12MHz to 25MHz.
XOUT
SEL3^
SEL2^
OE
12
13
11 10
9
8
14
PL602-3x
7
15
6
16
5
123 4
GND
CLKC
VDD
CLKT
BLOCK DIAGRAM
SEL[3:0]
XIN
XOUT
Oscillator
Amplifier
w/
integrated
load cap.
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
CLKC
CLKT
QFN-16L
^: Internal pull-up
*: On QFN package, PL602-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PL602-37/-39 have SEL0 (pin 10),
and pin11 is VDD. See pin assignment table for details.
Note: On QFN package there is a large center pad for thermal relief.
This pad needs to be connected to GND.
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PL602-3x
PL602-38
PL602-35
PL602-37
PL602-39
0 (Default) Output enabled
1
Tri-state
0
Tri-state
1 (Default) Output enabled
OE input: Logical states defined by LVPECL levels for PL602-38
Logical states defined by LVCMOS levels for PL602-37/-39
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 03/07/2012 Page 1