EVB7122 Datasheet, PDF (9/24 Pages) Melexis Microelectronic Systems – 27 to 930MHz Transceiver Evaluation Board Description

EVB7122
27 to 930MHz Transceiver
Evaluation Board Description
3.1.2 A – word
Name
RR
OPMODE
LNAGAIN
not used
TXPOWER
PACTRL
LOCKMODE
CPCUR
MODSEL
DTAPOL
IDLESEL
Bits
[9:0]
[11:10]
[12]
[13]
[15:14]
[16]
[17]
[18]
[19]
[20]
[21]
Description
4d .. 1023d
Reference divider ratio in RX operation mode
Operation mode
00 Standby mode
01 Receive mode
10 Transmit mode
11 Idle mode
#default
LNA gain
0 low LNA gain
1 high LNA gain
#default
This selection is valid if bit LNACTR (bit 21 in C-word) is set to internal LNA gain control.
set to ‘1’ for correct function
Output power steps
00 P1
01 P2
10 P3
11 P4
Set the PA-on condition
#default
0 PA is switched on if the PLL locks
1 PA is always on in TX mode
#default
Set the PLL locked state observation mode
0 before lock only
#default
Locked state condition will be ascertained only one time afterwards the LD signal remains in
high state.
1 before and after lock
locked state will be observed permanently
0 260 µA
1 1300 µA
Charge Pump output current
#default
Modulation mode
0 ASK
1 FSK
#default
This selection is valid if bit MODCTRL (bit 21 in D-word) is set to internal modulation
control.
Input data polarity
0 normal
#default
‘0’ for space at ASK or f_min at FSK, ‘1’ for mark at ASK or f_max at FSK
1 inverse
‘1’ for space at ASK or f_min at FSK, ‘0’ for mark at ASK or f_max at FSK
Active blocks in IDLE mode
0 only RO active
1 whole PLL active
#default
39012 07122 02
Rev. 005
Page 9 of 24
EVB Description
June/07