MLX16305 Datasheet, PDF (8/29 Pages) Melexis Microelectronic Systems – Interlock switch sensor interface IC

MLX16305
Interlock switch sensor interface IC
8.3. Voltage Regulation (SENSE)
The voltage on the SENSE pins is forced to the Vref level.
Depending on the applied Vref, the maximum deviation is specified as:
Vsense = Vref +/- Vsense_errx (see electrical specification)
• The Voltage regulation specification is only valid for Isense and Csense values within
specification.
• Maximum total capacitor load includes the wiring parasitic capacitance and Hall Switch supply
capacitor if applicable.
• The Output Settling time on pins SENSE1 … SENSE6 for the selected channel is Trise after
ENABLE pin is set high.
Vref
Supply voltage
of the selected
SENSE channel
0V
ENABLE
Trise
8.4. Output voltage to the microcontroller ADC (MEAS_OUT)
The microcontroller can evaluate/diagnose the state of the interlock switch based on the voltage that its
ADC will measure on the MEAS_OUT pin.
• The VMEASOUT output voltage is not higher than Vref + 0.5V to avoid damaging of the
microcontroller ADC input.
• The MEASOUT pin is able to deliver minimum IMEAS.
• MEAS_OUT can be made high impedant to allow multiplexing of 2 or more MLX16305 devices in
parallel when more than 6 channels are required.
3901016305
Rev. 005
Page 8 of 29
Data Sheet
Oct/06