MLX92251 Datasheet, PDF (4/13 Pages) Melexis Microelectronic Systems – Dual Hall Effect Latch with Speed & Direction

MLX92251LSE
Dual Hall Effect Latch with Speed & Direction
5 General Electrical Specifications
DC Operating Parameters T_A = -40°C to 150°C, V _DD = 2.7V to 24V (unless otherwise specified)
Parameter
Symbol Test Conditions
Min Typ ⁽¹⁾ Max Units
Supply Voltage
Supply Current
Reverse Supply Current
Output Leakage Current
Output Saturation Voltage
Output Rise/Fall Time ^(2,3)
Output Current Limit
Output ON Time under Current
Limit conditions⁽⁵⁾
Output OFF Time under Current
Limit conditions⁽⁵⁾
V_DD
I_DD
I_DDREV
I_OFF
V_OUTS
t _R / t_F
I_CL
t_CLON
Operating
V_DD = 12V
V_DD = -18V
V_OUT = 12V, V_DD = 12V, B < B_RP
B > B_OP, I_OUT = 10mA
V_DD = 12V, V_PU ⁽⁴⁾ = 5V,
R_PU = 1kΩ, C_L = 50pF
B > B_OP, V_OUT = 12V
B > B_OP, V_PU = 12V, R_PU = 100Ω
t_CLOFF B > B_OP, V_PU = 12V, R_PU = 100Ω
2.7
-
24 V
3
4.5
7 mA
1 mA
0.1 10 µA
0.2 0.5 V
0.1 0.3
1
µs
14 25 44 mA
150 230
µs
3.5
ms
Chopping Frequency
Speed Signal Delay ^(2,6)
Output Refresh Period
Output Jitter (p-p value) ⁽²⁾
Maximum Switching Frequency ^(2,7)
Power-On Time ⁽⁸⁾
f_CHOP
t_SPD
t_PER
t_JITTER
f_SW
t_PON
Over 1000 successive output
switching
events @1kHz square wave, B_PEAK=
50mT, t_RISE=t_FALL ≤100μs
≥30mT square wave magnetic field
V_DD= 5V, dV_DD/dt > 2V/µs
400
kHz
0.4 0.85 1.6 µs
3.2
5
8.4 µs
±2.6
µs
40 66
kHz
16 35 μs
Under-voltage Lockout Threshold
V_UVL
Under-voltage Lockout Reaction
time ⁽²⁾
t_UVL
2.2 2.4 2.7 V
1
µs
SE Package Thermal Resistance
R_TH
Single layer (1S) JEDEC board
300
°C/W
Table 2: electrical specifications
1 Typical values are defined at TA = +25ºC and VDD = 12V
2 Based on device characterization results, not subject to production test
3 Measured between 0.1*VPU and 0.9*VPU
4 RPU and VPU are respectively the external pull-up resistor and pull-up power supply
5 If the Output is in Current Limitation longer than tCLON the Output is switched off in high-impedance state. The Output returns back in active state at next reaching of
BOP or after tCLOFF time interval
6 Controlled delay between direction (DIR) signal update and speed (SP) signal update
7 Maximum switching frequency corresponds to the maximum frequency of the applied magnetic field which is detected without loss of pulses
8 The Power-On Time represents the time from reaching VDD = 2.7V to the first refresh of the SP output
390109225103
Rev 002
Page 4 of 13
Datasheet
April/13