EVB71121 Datasheet, PDF (3/18 Pages) Melexis Microelectronic Systems – 300 to 930MHz Receiver Evaluation Board Description

EVB71121
300 to 930MHz Receiver
Evaluation Board Description
1 Theory of Operation
1.1 General
The MLX71121 receiver architecture is based on a double-conversion super-heterodyne approach. The two
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency
is derived from a crystal (XTAL). As the first intermediate frequency (IF1) is very high, a reasonably high
degree of image rejection is provided even without using an RF front-end filter. At applications asking for
very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front
of the LNA. The second mixer MIX2 is an image-reject mixer.
The receiver signal chain is setup by one (or two) low noise amplifier(s) (LNA1, LNA2), two down-conversion
mixers (MIX1, MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required
modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or
the RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the
demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by
means of the positive and negative peak detectors (PKDET+/-). A digital post-processing of the sliced data
signal can be performed by a noise filter (NF) building block.
The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to
setup an LNA cascade (to further improve the input sensitivity). The two LNAs can also be setup to feed the
RF signal differentially.
PRELIMINARY ^{A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize}
power dissipation.
A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a
microcontroller. The clock output is open collector and gets activated through a load connected to positive
supply.
1.2 Technical Data Overview
! Input frequency ranges: 300 to 470MHz
610 to 930MHz
! Power supply range: 2.1 to 5.5V
! Temperature range: -40 to +125°C
! Image rejection:
65dB 1^st IF (with external RF front-end filter)
25dB 2^nd IF (internal image rejection)
! Maximum data rate: 50kps RZ (bi-phase) code,
! Shutdown current: 50 nA
100kps NRZ
! Operating current: 10.0 to 11.1mA
! Spurious emission: < -54dBm
! Internal IF: 1.8MHz with 300kHz 3dB bandwidth ! Linear RSSI range: > 60dB
! FM/FSK deviation range: ±10kHz to ±100kHz
! Crystal reference frequency: 16 to 27MHz
! MCU clock frequency: 2.0 to 3.4MHz
! Input Sensitivity: at 4kbps NRZ, BER = 3·10^-3
Frequency
315 MHz
433 MHz
868 MHz
915 MHz
FSK
internal IF2=1.8MHz, 300kHz BW,
Δf = ±20kHz
-107dBm
-107dBm
-104dBm
-102dBm
ASK
internal IF2=1.8MHz, 300kHz BW
-112dBm
-112dBm
-108dBm
-105dBm
Note: - Sensitivities given for RF input 1 (without SAW filter)
- Sensitivity for RF input 2 is about 2 to 3dB worse (because of SAW filter loss)
39012 71121 01
Rev. 003
Page 3 of 18
EVB Description
Jan/08