MLX83202 Datasheet, PDF (22/35 Pages) Melexis Microelectronic Systems – Automotive NFET pre-drivers

MLX83202/MLX83203
Automotive NFET pre-drivers
The 16 bit MISO/MOSI shift registers are controlled via 4 pins which are shared with other functions:
Pin
FETB1
FETB2
FETB3
ICOM_IN
SPI signal
MISO
CLK
MOSI
CSB
Comment
The signal on the MISO output is guaranteed to be stable while CLK is low
Clock input
The MOSI shift register is reading in data on the rising edge of CLK
Frames are defined by CSB low and have to consist of 16 clock pulses on CLK.
On the rising edge of CSB:
 If COMM_ERR=0 the read/write action is started as requested in the previous frame.
 Else (COMM_ERR = MISO[14]=1): a communication error is detected. No action will
occur (EE_READY latch will remain 0). This can be:
 Either due to a parity bit failure: MOSI[15] in frame N was incorrect.
 Or because less or more then 16 rising edges were received during CSB low of
frame N
CSB has to remain high until the read (T_EE_RD) / write (T_EE_WR) action is completed.
In this case EE_READY= MISO[13] bit in the next frame will be high
Else IF CSB goes low before the requested action is completed
 EE_READY= MISO[13] bit in the next frame will be low.
Table 12. SPI signals
3901083203
Rev 2.2
Page 22 of 35
Prelim. Data Sheet
4 Dec 2013