MLX80020 Datasheet, PDF (13/26 Pages) Melexis Microelectronic Systems – Enhanced LIN Transceiver

MLX80020
Enhanced LIN Transceiver
RxD
The pin RxD is a buffered open drain output with a typical load of:
Resistance: 2.7 kOhm
Capacitance: < 25 pF
The output signal supports by the external pull up resistor 3.3V and 5V supply systems.
TxD
The transmit data stream of the LIN protocol controller applied to the pin TxD is converted into the LIN bus
signal with slew rate control in order to minimize electromagnetic emissions.
The pin TxD contains a weak pull down resistor. The input thresholds are compatible to 3.3V and 5V supply
systems. To enable the transmit path, the TxD pin has to be driven recessive (HIGH) after or during the
normal mode has been entered.
TxD dominant time-out feature
By the first dominant level on pin TxD after the transmit path has been enabled, the dominant time-out
counter is started. In case of a faulty blocked permanent dominant level on pin TxD the transmit path will be
disabled after the specified time t_{TxD_to}. The time-out counter is reset by the first negative edge on pin TxD.
EN
The normal mode can be entered being in sleep or standby mode, when the pin EN is driven HIGH. To
prevent unwanted mode transitions, the EN input contains a debounce filter as specified (t_{EN_deb}).
The pin EN contains a weak pull down resistor. The input thresholds are compatible to 3.3V and 5V supply
systems.
Additionally the positive edge on pin EN results in an immediate reset of the active low interrupt on pin RxD
as well as the wake-up source recognition flag on pin TxD (see chapter 4.5 Wake Up).
MLX80020 – Datasheet
3901080020
Page 13 of 26
November 2015
Rev 006