TH71221 Datasheet, PDF (12/44 Pages) Melexis Microelectronic Systems – 27 to 930MHz FSK/FM/ASK Transceiver

TH71221
27 to 930MHz
FSK/FM/ASK Transceiver
Crystal
frequency f_RO
3.0000MHz
3.0000MHz
8.0000MHz
8.0000MHz
8.0000MHz
Frequency
resolution f_R
2.93kHz
2.93kHz
12.5kHz
25kHz
250kHz
R
counter
1023
1023
640
320
32
N
counter
13107
131071
35812
34746
3660
Operating
frequency f_VCO
38.437MHz
384.372MHz
447.65MHz
868.65MHz
915.0MHz
3.1.5 Phase-Frequency Detector
The phase-frequency detector creates an error voltage proportional to the phase difference between the
reference signal f_R and f_N. The implementation of the phase detector is a phase-frequency type. That circuitry
is very useful because it decreases the acquisition time significantly. The gain of the phase detector can be
expressed as:
K _PD =
I _CP
2π
,
(7)
where I_CP is the charge pump current which is set via register CPCUR. In the TH7122 design the VCO
frequency control characteristic is with negative polarity. This means the VCO frequency increases if the loop
filter output voltage decreases and vice versa. When an external varactor diode is added to the VCO tank,
the tuning characteristic can be changed between positive and negative depending on the particular varactor
diode circuitry. Therefore the PDFPOL register can be used to define the phase detector polarity.
3.1.6 Lock Detector
In Programmable User Mode a lock-detect signal LD is available at pin FS1/LD (pin 19). The lock detection
circuitry uses Up and Down signals from the phase detector to check them for phase coherency. Figure 4
shows an overview of the lock signal generation. The locked state and the unlock condition will be decided
on the register settings of LDTM and ERTM respectively. In the start-up phase of the PLL, Up and Down
signals are quite unbalanced and counter CNT_LD receives no clock signal. When the loop approaches
steady state, the signals Up and Down begin to overlap and CNT_LD counts down. Herein register LDTM
sets the number of counts which are necessary to set the lock detection signal LD. If an unlock condition
occurs, the counter CNT_LD will be reloaded and therefore its CARRY falls back.
LDTM [1 : 0]
Up
Down
PFD
ERTM [1 : 0]
F_RO
RO
2
&
=
2
D CARRY
&
CR
LOAD
CNT_LD
D CARRY
&
CR
LOAD
CNT_ER
Control
Logic
RESET LD
LOCKMODE
RQ
S
LD
MUX
Fig. 4: Lock Detection Circuit
39010 071221
Rev. 005
Page 12 of 44
Data Sheet
June/07