TH8080 Datasheet, PDF (11/23 Pages) Melexis Microelectronic Systems – SoloLIN Transceiver

TH8080
SoloLIN Transceiver
RxD Output
The data signals from the BUS pin will be transferred continuously to the pin RxD. Short spikes on the bus
signal are suppressed by the implemented debouncing circuit.
VS
60%
BUS 50%
40%
RxD
VBUS_CNT_max
VhHYS
VBUS_CNT_min
t < t_{rec_deb}
t < t_{rec_deb}
Figure 6 - Receive impulse diagram
The receive threshold values V_{BUS_CNT_max} and V_{BUS_CNT_min} are symmetrical to the centre voltage of 0.5*V_S
with a hysteresis of typ. 0.175*V_S. Including all tolerances the LIN specific receive threshold values of 0.4*V_S
and 0.6*V_S will be secure observed.
The received BUS signal will be output to the RxD pin:
BUS < V_{BUS_CNT} – 0.5 * V_HYS ->
BUS > V_{BUS_CNT} + 0.5 * V_HYS ->
RxD = low (BUS dominant)
RxD = high, floating (BUS recessive)
This pin is a buffered open drain output with a typical load of:
Resistance: 2.7 kOhm
Capacitance: < 25 pF
Datarate
The TH8080 is a constant slew rate transceiver that means the bus driver operates with a fixed slew rate
range of 0.5 V/µs ≤ ∆V/∆T ≤ 3V/µs. This principle secures a very good symmetry of the slope times between
recessive to dominant and dominant to recessive slopes within the LIN bus load range (C_BUS, R_term).
The TH8080 guarantees data rates up to 20kbit within the complete bus load range under worst case
conditions. The constant slew rate principle is very robust against voltage drops and can operate with RC-
oscillator systems with a clock tolerance up to ±2% between 2 nodes.
TH8080 – Datasheet
3901008080
Page 11 of 23
July 2004
Rev 006