MLC852P Datasheet, PDF (7/35 Pages) Megawin Technology Co., Ltd – single chip 8-bit micro-controller

Dividers
Divider0 is a 7-bit up-counter. The clock source is from Fosc. It could be reset to 00H by POR,
system reset or waked from stop mode. Certain intermediary signals of the divider 0 could be the
clock source of timer0.
Fosc
Divider 0
P0.5
Fosc
Fosc/2
Fosc/4
Fosc/32
Fosc/128
timer 0
TM0X
Divider1:
Divider1 is a 14-bit up-counter. The clock source is from sub-oscillator (32 KHz). It could be reset to
0000H by POR, system reset or waked from stop mode. DIV1x_sel could select the source of
interrupt.
Address
1203H
Name
DIV1x_SEL
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2 Bit 1 _{Bit 0} R W
- CKO1 CKO0 √ √
CKO1
0
0
1
1
CKO0
0
1
0
1
Selected DIV1x frequency
Fx32/256 (128Hz)
Fx32/128 (512Hz)
Fx32/8 (4096Hz)
unused
The default clock source is F_x32/256 (128Hz)
Divider 1
2Hz
128Hz
512Hz
4096Hz
DIV1X_SEL
2HzX
DIV1X
MEGAWIN
MLC852P Technical Summary
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