MG64F225 Datasheet, PDF (43/68 Pages) Megawin Technology Co., Ltd – Flash write/erase cycle

Bit[1:0] : EPINX[1:0] -- Endpoint Index Bits [2:0]
2’b00: Function Endpoint 0. (Default)
2’b01: Function Endpoint 1.
2’b10: Function Endpoint 2.
2’b11: Reserved.
MG64F225 Datasheet
V1.00
EPCON (Endpoint Control Register, Endpoint-Indexed, Address=21H, SYS_RST / USB_RST, Read/Write)
7
6
5
4
3
2
1
0
RXSTL
TXSTL
--
--
--
RXEPEN
--
TXEPEN
R/W
R/W
R/W
R/W
Endpoint 0 (EPINDEX=0)
Bit7 : RXSTL -- Receive Endpoint Stall.
0: Disable. (Default)
1: Enable.
Note : Clear this bit only when the host has intervened through commands sent down endpoint 0. When
this bit is set and RXSETUP is clear, the receive endpoint will respond with a STALL handshake to a
valid OUT token. When this bit is set and RXSETUP is set, the receive endpoint will NAK. This bit
does not affect the reception of SETUP tokens by a control endpoint.
Bit6 : TXSTL -- Transmit Endpoint Stall.
0: Disable. (Default)
1: Enable.
Note : Clear this bit only when the host has intervened through commands sent down endpoint 0. When
this bit is set and RXSETUP is clear, the transmit endpoint will respond with a STALL handshake to a
valid IN token. When this bit is set and RXSETUP is set, the transmit endpoint will NAK.
Bit[5:3] : Reserved.
Bit2 : RXEPEN -- Receive Endpoint Enable.
0: Disable.
1: Enable. (Default)
Bit1 : Reserved.
Bit0 : TXEPEN -- Transmit Endpoint Enable.
0: Disable.
1: Enable. (Default)
Endpoint 1 (EPINDEX=1)
Bit7 : Reserved.
Bit6 : TXSTL -- Transmit Endpoint Stall.
0: Disable. (Default)
1: Enable.
Bit[5:1] : Reserved.
Bit0 : TXEPEN -- Transmit Endpoint Enable.
0: Disable. (Default)
1: Enable.
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2013 All right reserved.
QP-7300-03D
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