MG74PG1B08 Datasheet, PDF (33/128 Pages) Megawin Technology Co., Ltd – Keypad Interrupt function on all GPIO

10.6. WDT Reset
When WDT is enabled to start the counter, WDTF will be set by WDT overflow. If WREN (WDTCR.7) is enabled, the
WDT overflow will trigger a system reset that causes CPU to restart. Software can read the WDTF to recognize the
WDT reset occurred.
PCON1: Power Control Register 1
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x97
POR = 00xx-0000
7
6
5
4
3
SWRF
EXRF
--
--
KBIF
R/W
R/W
W
W
R/W
2
BOF1
R/W
1
BOF0
R/W
0
WDTF
R/W
Bit 0: WDTF, WDT Overflow/Reset Flag.
0: This bit must be cleared by software writing “1” on it. Software writing “:0” is no operation.
1: This bit is only set by hardware when WDT overflows. Writing “1” on this bit will clear WDTF. If WREN (WDTCR.7)
is set, WDTF indicates a WDT Reset occurred.
WDTCR: Watch-Dog-Timer Control Register
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0xE1
POR = 0000-0000 (xxx0_xxxx by Hardware Option)
7
6
5
4
3
2
1
0
WREN
NSW
ENW
CLRW
WIDL
PS2
PS1
PS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7: WREN, WDT Reset Enable. The initial value can be changed by hardware option, WRENO.
0: The overflow of WDT does not set the WDT reset. The WDT overflow flag, WDTF, may be polled by software or
trigger an interrupt.
1: The overflow of WDT will cause a system reset. Once WREN has been set, it cannot be cleared by software in
normal page. In protected-write mode, software can modify it to “0” or “1”.
MEGAWIN
MG74PG1B08 Data Sheet
33