MG65PG5A08A Datasheet, PDF (31/48 Pages) Megawin Technology Co., Ltd – Build-in a watchdog timer

MG65PG5A08A Datasheet
Version 2.01
15 Configurable I/O Ports
15.1 Port 0
15.1.1 Port 0 Port
Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W
00E4H
P0port
P07 P06 P05 P04 P03 P02 P01 P00 √ -
Port 0 is combined with 8-bit I/O port. P0.7~P0.0 can be programmed as input or output individually. When P0.n is
configured as an output pin, the P0.n pin would output the logic content of internal P0obuf.n (P0 output buffer). The
default value of P0obuf is 00000000b.
When the P0.n is configured as output mode, reading P0.n would always read logic ‘0’.
When the P0.n is configured as input mode, reading P0.n would always read the logic value from pad.
15.1.2 Port 0 Output Buffer
Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W
00E4H
P0obuf
P07 P06 P05 P04 P03 P02 P01 P00 - √
This register is used to buffer the output value of P0.7 ~ P0.0 in output mode and it is write-only.
※ Bit-manipulation instructions are not available on this register.
15.1.3 Port 0 Direction Register
Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W
00E5H
P0dir
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 - √
P0_DR (Port 0 Direction)
P0_DR.n = 0: P0.n is configured as an input pin. (Default)
1: P0.n is configured as an output pin.
※ Bit-manipulation instructions are not available on this register.
15.1.4 Port 0 Pull-high Control Register
Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W
00E6H
P0plh
PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 - √
1: Enable internal pull-high (default); 0: Disable internal pull-high
PHn: Control bit is used to enable the pull-high of P0.n pin.
※ Bit-manipulation instructions are not available on this register.
15.1.5 Port 0 Analog Function Control Register
Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W
00E7H
P0an
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 - √
0: Normal I/O function; 1: Analog function
MFn: Control bit is used to P0.n function selection.
※ Bit-manipulation instructions not available on this register.
15.1.6 Port 0 Interrupt Edge Select Register
Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W
00E8H
P0es
ES7 ES6 ES5 ES4 ES3 ES2 ES1 ES0 - √
0: Falling edge; 1: Rising edge
MFn: Control bit is used to P0.n interrupt edge selection.
※ Bit-manipulation instructions not available on this register.
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
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