MG65L566A Datasheet, PDF (18/30 Pages) Megawin Technology Co., Ltd – Watchdog timer built-in

MG65L566A Datasheet
Version 2.1
11 Timer
11.1 Timer0
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
00C8H
TM0
T7
T6
T5
T4
T3
T2
T1
00CAH
TM0_CTL STC RL/S
-
-
-
TCS0 TKI1
Timer 0 is an 8-bit down-count counter.
STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock
RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload
TCS0: select the input clock source of timer0. 0:F_OSC, 1: F_X32
Bit 0
T0
TKI0
RW


TKI1
0
0
1
1
TKI0
0
1
0
1
Selected TM0 input frequency (F_{TM0_DIV})
F_TM0 / 1
F_TM0 / 2
F_TM0 / 16
F_TM0 / 64
F_{TM0_UV}, can be calculated with the equation:
F_{TM0_UV} = F_TM0 / (TM0+1), where the F_TM0 is the timer input frequency set by TKI1 and TKI0.
For example: (if F_TM0 = 2.000MHz, TKI1=TKI0=0)
TM0
Frequency
00H
Reserved
01H
1.000MHz
02H
667kHz
…
…
FFH
7.84kHz
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
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