MG69L331 Datasheet, PDF (17/28 Pages) Megawin Technology Co., Ltd – Single Chip 8-bit CPU

MG69L331 Datasheet
Version 2.0
10 Divider
10.1 Divider
Divider (The example is base on 3. 579545MHz)
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
DIVlow
13984 227968 55937 111875 223750
DIVhigh
874
Bit 2
447500
1748
Bit 1
895000
3496
Unit: Hz
Bit 0 R W
1790000 _{- -}
6992
The time-out period is obtained by the equation: 4096/OSC.
The DIV flag will be set when 4096/OSC or 256/OSC (selected by DIVsel) is met.
Cloc
k
Clock/x
To TM0
Divider (12-bit)
R
Clock/4096
Pulse
generator
Sys_rst or
CPU STOP=1
Data
Bus
Data bus_bit4
Write
EVTclr
S
D
Q
CR
Sys_rst
DIVevt
Read
EVTflag
Divider Architecture
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
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