MLC331B Datasheet, PDF (14/30 Pages) Megawin Technology Co., Ltd – Single chip 8-bit CPU

Watchdog Timer (WDT)
Address
00DEH
00DFH
Name
WDT_CTL
WDT_CLR
Bit 7
RSTS
CLR
Bit 6
-
-
Bit 5
-
-
Bit 4
-
-
Bit 3
-
Bit 3
Bit 2
RSEL
Bit 2
Bit 1
CKI1
Bit 1
Bit 0
CKI0
Bit 0
RW
√√
√√
RSTS: WDT reset status, set by hardware when WDT overflows, clear by hardware reset or set WDT_CLR.7 to
one to clear this bit (this bit is read only)
RSEL: WDT reset selector, = 0 Reset whole chip except RSTS (WDT_CTL.7)
= 1 Reset PC and IRQ_EN only
CKI1, CKI0: WDT clock selector, = 00 FDIV1/16384 selected (8 S @ FDIV1 = 32K)
= 01 FDIV1/4096 selected (2 S @ FDIV1 = 32K)
= 10 FDIV1/1024 selected (0.5 S @ FDIV1 = 32K)
= 11 FDIV1/128 selected (62.5 mS @ FDIV1 = 32K)
CLR: RSTS clear control bit, program can clear RSTS by program "1" into this bit (this bit is write only)
The watchdog timer (WDT), which is organized as a 4-bit counter, is designed to prevent the program
from unknown errors. The WDT is enabling by code option. If the WDT overflows, the WDT reset
function will be performed. The watchdog timer control register (WDT_CTL) controls the WDT reset
function. RSTS (WDT_CTL.7) is set by hardware when the WDT overflows and is cleared by store
one to the bit 7 of WDT_CLR register or hardware reset. There are two types of WDT reset, which is
selected by RSEL (bit2 of WDT_CTL). WDT overflow will cause two types reset depending on the
setting of RSEL  if RSEL is equal to 0, the reset is the same as hardware reset except the setting of
WDT_CTL and WDT_CLR; If RSEL is equal to 1, the reset only acts on program counter (PC) and
IRQ_EN. The WDT clock frequency is decided by bit1 and bit0 of WDT_CTL register. Store one to the
bit 7 of WDT_CLR register will also reset the contents of the WDT. In normal operation, the
application program must reset WDT before it overflows. The organization of the divider1 and
watchdog timer is shown as below.
WDT_CTL.0
WDT_CTL.1
Fdiv1/128
Fdiv1/1024
(Option code = 0)
Disable
Fdiv1/4096
Fdiv1/16384
Enable
(Option code = 1)
WDT
Qw1 Qw2 Qw3 Qw4
R
R
R
R
WDT_CTL.2
Overflow signal
System Reset
except WDT_CTL.7
S
Q
R
PC & IRQ_EN reset
(other peripheral unchanged)
WDT_CTL.7
Hardware reset
WDT_CLR <- 8XH
Fdiv1
... Q1 Q2
Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16
Divider1
14
MLC0xxB Series Technical Summary
MEGAWIN