MG69M220 Datasheet, PDF (12/27 Pages) Megawin Technology Co., Ltd – Single Chip 8-bit CPU

MG69M220 Datasheet
Version 1.09
7 Interrupt
MG69M220 provides five kinds of interrupt sources. The flag IRQ_EN and IRQ_ST are used to control the
interrupts. When flag IRQ_ST is set to ‘1’ by hardware and the corresponding bits of flag IRQ_EN has been set by
software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the CLI or STA
IRQ_EN, # I instruction is invoked. Executing the SEI instruction can also disable the interrupts.
Vector Address
FFFEH, FFFFH
FFFCH, FFFDH
Item
P1 IRQ
P0 IRQ
TM0 IRQ
TM1 IRQ
DIV IRQ
RESET
WDT
LVR
Table 7-1 Interrupt Vector Table
Flag
Properties
Memo
IRQ_ST.1
Ext.
P1.0 ~ P1.4 interrupt vector
IRQ_ST.2
Ext.
P0.0 ~ P0.7 interrupt vector
IRQ_ST.3
Int.
TM0 underflow interrupt
IRQ_ST.4
Int.
TM1 underflow interrupt
IRQ_ST.5
Int.
Divider carry out interrupt
None
Ext.
Initial reset
IRQ_ST.7
Int.
Watch dog timer reset
None
Int.
Low voltage reset
7.1 Interrupt Register
IRQ enable flag
Address
Name
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
00C2H
IRQ_EN PDBOR
-
DIVx TM1 TM0 P0
P1
Program can enable or disable the ability of triggering IRQ through this register.
0: Disable (default “0” at initialization)
1: Enable
P0: Falling edge occurs at port 0 input mode
P1: Falling edge occurs at port 1
TM0: Timer 0 underflow
TM1: Timer 1 underflow
DIVx: Divider selected interrupt frequency occurred
PDBOR: Power down BOR function
Bit 0 ^{R W}
-
-
IRQ status flag
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 _{Bit 0} R W
00C2H
IRQ_ST WDT
-
DIVx TM1 TM0 P0
P1
-
-
When IRQ occurs, program can read this register to know which source is triggering IRQ. If the interrupt triggering
is enabled and the interrupt event is accepted, the corresponding IRQ status flag should be cleared by program
after the interrupt vector is loaded into program counter.
IRQ clear flag
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 _{Bit 0} R W
00C3H
IRQ_CLR WDT
-
DIVx TM1 TM0 P0
P1
-
-
Program can clear the interrupt event by writing ‘1’ into the corresponding bit. The IRQ_CLR.7 (WDT) is protected by CWPR.
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
12/27