MDT10P55B Datasheet, PDF (6/11 Pages) List of Unclassifed Manufacturers – MDT10P55B

MDT10P55B
(B) Program Memory
Address
Description
000-3FF
Program memory
000
The starting address of power on, external reset or WDT time-out reset.
8. Reset Condition for all Registers
Register
Address
Power-On Reset
/MCLR Reset
CPIO B
--11 1111
--111 1111
CPIO C
--11 1111
--11 1111
TMR
1111 1111
1111 1111
IAR
00h
xxxx xxxx
uuuu uuuu
RTCC
01h
xxxx xxxx
uuuu uuuu
PC
02h
0000 0000
0000 0000
STATUS
03h
0001 1xxx
#00# #uuu
MSR
04h
110x xxxx
11uu uuuu
PORT B
06h
--xx xxxx
--uu uuuu
PORT C
07h
--xx xxxx
--uu uuuu
Note : u unchanged, x unknown, - unimplemented, read as “0”
# value depends on the condition of the following table
WDT Reset
--11 1111
--11 1111
--11 1111
uuuu uuuu
uuuu uuuu
0000 0000
#00# #uuu
11uu uuuu
--uu uuuu
--uu uuuu
Condition
/MCLR reset (not during SLEEP)
/MCLR reset during SLEEP
WDT reset (not during SLEEP)
WDT reset during SLEEP
Wake-up from SLEEP on pin change
Status: bit 7
0
0
0
0
1
Status: bit 4
u
1
0
0
1
Status: bit 3
u
0
1
0
0
9. Instruction Set :
Instruction Code
010000 00000000
010000 00000001
010000 00000010
010000 00000011
010000 00000100
Mnemonic
Operands
NOP
CLRWT
SLEEP
TMODE
RET
Function
No operation
Clear Watchdog timer
Sleep mode
Load W to TMODE register
Return
Operating
None
0 WT
0 WT, stop OSC
W TMODE
Stack PC
Status
TF, PF
TF, PF
None
None
This specification are subject to be changed without notice. Any latest information please preview
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P. 6
2005/6 Ver. 1.2