MX25L3275E Datasheet, PDF (74/87 Pages) Macronix International – 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25L3275E
Symbol
tW
tBP
tPP
tSE
tBE
tBE
tCE
tWPS
tWSR
Alt. Parameter
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
Write Protection Selection Time
Write Security Register Time
Min.
Typ.
12
0.7
30
0.14
0.25
10
Max.
Unit
40
ms
50
us
3
ms
200
ms
1.6
s
2
s
50
s
1
ms
1
ms
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. The value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. For 4READ instruction, when dummy cycle=6, clock rate is 86MHz (default), and when dummy cycle=8, clock
rate is 104MHz.
P/N: PM1830
REV. 1.2, NOV. 07, 2013
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