MX25U12835F Datasheet, PDF (59/96 Pages) Macronix International – 1.8V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25U12835F
9-24. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before
sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3 as address and data input, which can improve programmer performance and the effectiveness of application.
The 4PP operation frequency supports as fast as 104MHz. The other function descriptions are as same as standard
page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
Figure 55. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)
CS#
SCLK
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Command
6 ADD cycles
Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4
SIO0
38h
A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 D4 D0 D4 D0
SIO1
A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 D5 D1 D5 D1
SIO2
A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 D6 D2 D6 D2
SIO3
A23 A19 A15 A11 A7 A3 D7 D3 D7 D3 D7 D3 D7 D3
P/N: PM1728
REV. 1.4, FEB. 12, 2014
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