MX25L3235E Datasheet, PDF (53/87 Pages) Macronix International – 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

MX25L3235E
10-28. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN instruction is required
before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for
customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area
cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes
high.
The SIO[3:1] are don't care when during this mode.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 31. Write Security Register (WRSCUR) Sequence (Command 2F)
CS#
SCLK
SI
SO
01234567
Command
2F
High-Z
10-29. Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If
WPSEL=0, flash is under BP protection mode. If WPSEL=1, flash is under individual block protection mode. The
default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an
OTP bit. Once WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on
BP mode, the individual block protection mode is disabled. Contrarily, if flash is on the individual block protection
mode, the BP mode is disabled.
The SIO[3:1] are don't care when during this mode.
Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1,
all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via
SBULK and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is
conducted.
BP protection mode, WPSEL=0:
ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is
bit 7 of status register that can be set by WRSR command.
P/N: PM1773
REV. 1.5, NOV. 06, 2013
53