MX25L25735F Datasheet, PDF (50/96 Pages) Macronix International – 3V 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

MX25L25735F
10-18. Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in SPI mode, 3FFh data cycle(10 clocks in 4-byte
address mode), should be issued in 1I/O sequence. In QPI Mode, FFFFFFFFFFh data cycle (10 clocks in 4-byte
address mode), in 4I/O should be issued.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 39. Performance Enhance Mode Reset for Fast Read Quad I/O using 4Byte Address Sequence (SPI
Mode)
CS#
Mode 3
SCLK _{Mode ̌}
Mode Bit Reset
for Quad I/O
0 1 2 34 5 6 78 9
Mode 3
Mode ̌
SIO0
3FFh
SIO1
Don’t Care
SIO2
Don’t Care
SIO3
Don’t Care
Figure 40. Performance Enhance Mode Reset for Fast Read Quad I/O using 4Byte Address Sequence (QPI
Mode)
CS#
Mode 3
SCLK _{Mode ̌}
Mode Bit Reset
for Quad I/O
0 1 2 3 4 5 6 78 9
Mode 3
Mode ̌
SIO[3:0]
FFFFFFFFFFh
P/N: PM1799
REV. 1.2, OCT. 31, 2013
50