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MX25L12855FXDI-10G Datasheet, PDF (46/101 Pages) Macronix International – DATASHEET | |||
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MX25L12855F
9-17. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
Performance enhance mode is supported in both SPI and QPI mode.
In QPI mode, âEBhâ and SPI âEBhâ commands support enhance mode. The performance enhance mode is not sup-
ported in dual I/O mode.
To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer
toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.
Issuing âFFhâ command can also exit enhance mode. The system then will leave performance enhance mode and
return to normal operation.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes lowâsending 4
READ instructionâ3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 âperformance enhance toggling bit
P[7:0]â 4 dummy cycles (Default) âdata out still CS# goes high â CS# goes low (reduce 4 Read instruction) â
3-bytes random access address.
P/N: PM1877
REV. 1.0, OCT. 23, 2012
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