MX25L12855E Datasheet, PDF (46/70 Pages) Macronix International – 128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY

MX25L12855E
Figure 13. Read Identification (RDID) Sequence (Command 9F)
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31
Command
9F
High-Z
Manufacturer Identification
Device Identification
7 65
MSB
3 2 1 0 15 14 13
MSB
3210
Figure 14. Read Identification (RDID) Sequence (Parallel)
CS#
SCLK
SI
PO7~0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Command
9F
High-Z
Manufacturer Identification
Device Identification
Notes :
1. Under parallel mode, the fastest access clock freg. will be changed to 6MHz(SCLK pin clock freg.)
To read identification in parallel mode, which requires a parallel mode command (55h) before the read identifica-
tion command. To exit parallel mode, it requires a (45h) command or power-off/on sequence.
2. There are 3 data bytes which would be output sequentially for Manufacturer and Device ID 1'st byte (Memory
Type) and Device ID 2'nd byte (Memory Density).
P/N: PM1466
REV. 0.05, MAR. 05, 2009
46