MX25L12875FM2I-10G Datasheet, PDF (40/102 Pages) Macronix International – DATASHEET

MX25L12875F
9-12. Dual Output Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-
tion, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte address on
SIO0→ 8 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 28. Dual Read Mode Sequence
CS#
SCLK
SI/SIO0
SO/SIO1
0123456789
30 31 32
39 40 41 42 43 44 45
Command
3B
…
24 ADD Cycle
… _{A23 A22}
A1 A0
…
Configurable
Dummy Cycle
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
High Impedance
D7 D5 D3 D1 ^{D7 D5}
P/N: PM1855
REV. 1.1, OCT. 31, 2013
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