MX25U6435E Datasheet, PDF (37/83 Pages) Macronix International – 64M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

MX25U6435E
Figure 11. The individual block lock mode is effective after setting WPSEL=1
4KB
4KB
TOP 4KBx16
Sectors
4KB
64KB
Uniform
64KB blocks
Bottom
4KBx16
Sectors
64KB
4KB
4KB
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
• Power-Up: All SRAM bits=1 (all blocks are default protected).

All array cannot be programmed/erased
• SBLK/SBULK(36h/39h):
- SBLK(36h): Set SRAM bit=1 (protect) : array can not be
programmed/erased
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
programmed/erased
- All top 4KBx16 sectors and bottom 4KBx16 sectors
and other 64KB uniform blocks can be protected and
unprotected SRAM bits individually by SBLK/SBULK
command set.
• GBLK/GBULK(7Eh/98h):
- GBLK(7Eh): Set all SRAM bits=1,whole chip are protected
and cannot be programmed/erased.
- GBULK(98h): Set all SRAM bits=0,whole chip are
unprotected and can be programmed/erased.
- All sectors and blocks SRAM bits of whole chip can be
protected and unprotected at one time by GBLK/GBULK
command set.
• RDBLOCK(3Ch):
- use RDBLOCK mode to check the SRAM bits status after
SBULK /SBLK/GBULK/GBLK command set.
SBULK / SBLK / GBULK / GBLK / RDBLOCK
P/N: PM1561
REV. 1.5, NOV. 07, 2013
37