MX25U3235E Datasheet, PDF (33/86 Pages) Macronix International – 32M-BIT [x 1/x 2/x 4] 1.8V CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25U3235E
9-19. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the current is
reduced from standby to deep power-down). The Deep Power-down mode requires the Deep Power-down (DP)
instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase
instruction are ignored.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode. (Please refer to "Figure 50. Deep Power-down (DP) Sequence (Command B9) (SPI Mode)"
and "Figure 51. Deep Power-down (DP) Sequence (Command B9) (QPI Mode)")
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being
reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and
when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the
byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.
As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.
9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in "Table 15. AC Characteristics". Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The
RDP instruction is only for releasing from Deep Power Down Mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 9. ID
Definitions" on next page. This is not the same as RDID instruction. It is not recommended to use for new design.
For new design, please use RDID instruction.
The sequence is shown as "Figure 52. RDP and Read Electronic Signature (RES) Sequence (Command AB) (SPI
Mode)", "Figure 53. Release from Deep Power-down (RDP) Sequence (Command AB) (SPI Mode)" and "Figure 54.
Release from Deep Power-down (RDP) Sequence (Command AB) (QPI Mode)". Even in Deep power-down mode,
the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write
cycle; there's no effect on the current program/erase/write cycle in progress.
SPI (8 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if
continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep
Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-
down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max).
Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction.
P/N: PM1472
REV. 1.9, NOV. 11, 2013
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