MX29LA129MH Datasheet, PDF (3/71 Pages) Macronix International – 128M-BIT SINGLE VOLTAGE 3V ONLY UNIFORM SECTOR FLASH MEMORY

PIN CONFIGURATION
56 TSOP
A22
1
CE1
2
A21
3
A20
4
A19
5
A18
6
A17
7
A16
8
VCC
9
A15
10
A14
11
A13
12
A12
13
CE0
14
WP#/ACC
15
RESET#
16
A11
17
A10
18
A9
19
A8
20
GND
21
A7
22
A6
23
A5
24
A4
25
A3
26
A2
27
A1
28
MX29LA129M H/L
56
NC
55
WE#
54
OE#
53
RY/BY#
52
Q15
51
Q7
50
Q14
49
Q6
48
GND
47
Q13
46
Q5
45
Q12
44
Q4
43
VI/O
42
GND
41
Q11
40
Q3
39
Q10
38
Q2
37
VCC
36
Q9
35
Q1
34
Q8
33
Q0
32
A0
31
BYTE#
30
A23
29
CE2
PIN DESCRIPTION
SYMBOL PIN NAME
A0
Byte-Select Address
A1~A23 Address Input
Q0~Q15 Data Inputs/Outputs
CE0~CE2 Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
RESET# Hardware Reset Pin, Active Low
WP#/ACC Hardware Write Protect/Programming
Acceleration input
RY/BY# Read/Busy Output
BYTE# Selects 8 bit or 16 bit mode
VCC
+3.0V single power supply
VI/O
Output Buffer Power (2.7V~3.6V this
input should be tied directly to VCC )
GND
Device Ground
NC
Pin Not Connected Internally
LOGIC SYMBOL
24
A0-A23
16 or 8
Q0-Q15
CEx
OE#
WE#
RESET#
WP#/ACC
BYTE#
VI/O
RY/BY#
Chip Enable Truth Table
CE2
CE1
CE0
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIH
VIL
VIH
VIH
VIH
VIL
VIH
VIH
VIH
DEVICE
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
Note: For Single-chip applications, CE2 and CE1 can be
strapped to GND.
P/N:PM1171
REV. 1.0, FEB. 27, 2006
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