MX29GL320EHT2I-70G Datasheet, PDF (26/77 Pages) Macronix International – DATASHEET

MX29GL320E T/B
MX29GL320E H/L
COMMAND OPERATIONS (cont'd)
SECTOR ERASE (cont'd)
The system can determine the status of the embedded sector erase operation by the following methods:
Status
Time-out period
In progress
Exceeded time limit
Q7
Q6
Q5
0
Toggling
0
0
Toggling
0
0
Toggling
1
Q3^*1
Q2
RY/BY#^*2
0
Toggling
0
1
Toggling
0
1
Toggling
0
Note:
1. The Q3 status bit is the 50us time-out indicator. When Q3=0, the 50us time-out counter has not yet reached
zero and a new Sector Erase command may be issued to specify the address of another sector to be erased.
When Q3=1, the 50us time-out counter has expired and the Sector Erase operation has already begun. Erase
Suspend is the only valid command that may be issued once the embedded erase operation is underway.
2. RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor.
3. When an attempt is made to erase only protected sector(s), the erase operation will abort thus preventing any
data changes in the protected sector(s). Q7 will output "0" and Q6 will toggle briefly (100us or less) before
aborting and returning the device to Read mode. If unprotected sectors are also specified, however, they will
be erased normally and the protected sector(s) will remain unchanged.
4. Q2 is a localized indicator showing a specified sector is undergoing erase operation or not. Q2 toggles when
user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase
suspend mode).
CHIP ERASE
The Chip Erase operation is used erase all the data within the memory array. All memory cells containing a "0"
will be returned to the erased state of "1". This operation requires 6 write cycles to initiate the action. The first
two cycles are "unlock" cycles, the third is a configuration cycle, the fourth and fifth are also "unlock" cycles, and
the sixth cycle initiates the chip erase operation.
During the chip erase operation, no other software commands will be accepted, but if a hardware reset is re-
ceived or the working voltage is too low, that chip erase will be terminated. After Chip Erase, the chip will auto-
matically return to Read mode.
The system can determine the status of the embedded chip erase operation by the following methods:
Status
In progress
Exceed time limit
Q7
Q6
Q5
Q2
RY/BY#^*1
0
Toggling
0
Toggling
0
0
Toggling
1
Toggling
0
*1: RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor.
P/N:PM1509
REV. 1.5, OCT. 21, 2015
26