MX98726 Datasheet, PDF (23/55 Pages) Macronix International – SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

Host Receive Packet Counter : Reserved, RO
Bit
52.7-0
53.7-0
Symbol
Reserved
Reserved
Host DMA Fragment Counter : Reserved, RW
Bit
54.7-0
55.7-0
56.7-0
Symbol
Reserved
Reserved
Reserved
MX98726
4.0 Host Communication
GMAC and the device driver communicate through three
data structures :
* On chip registers described in Chapter 3.
* Descriptor and data buffer resides in packet memory.
* Direct IO port to on chip TX FIFO for direct packet
transmission.
GMAC moves received data frames to the receive buffer
in the local packet memory and transmits data from the
transmit buffers in the local packet memory. All the page
pointers in the registers together with the descriptors
acts as pointers to these buffers in the packet memory.
Figure 4.0 depict the general data structure of packet
memory and page pointers.
There are two data buffers inside the packet memory,
i.e. transmit buffer and receive buffer. Packet memory
is partitioned into pages, each page contains exactly
256 bytes. A page pointer defined by registers acts as
the base address of the corresponding page. By pro-
gramming these page pointers, size and area of trans-
mit buffer and receive buffer can be individually set to
desirable size and area.
The transmit and receive buffers must be contiguous
and separated by the BP ( Boundary Page pointer ) de-
fined in registers 0Ah and 0Bh. TLBP ( Transmit Low
Boundary Pointer ) defines the start page of the trans-
mit buffer. BP- 1 defines the end page of the transmit
buffer. If the current transmit process exceeds the end
of BP- 1 page then it will be set to the start page pointed
by TLBP, thus forms a "ring buffer" that logically links
the end page back to the start page of transmit buffer.
Receive buffer has a similar structure as transmit buffer.
The start page of receive buffer is pointed to by BP while
the end page is pointed to by RHBP ( Receive High
Boundary Page Pointer ). If current receive process
exceeds the end of the end page pointed by RHBP, then
it will be set to the start page pointed by BP, thus forms
a "ring buffer" that logically links the end page and the
start page of receive buffer.
A 1.6K bytes TX FIFO can also be used to send out a
packet directly from FIFO. Register port 48h can be used
by host to write packet data directly into TX FIFO. After
moving the last byte into the TX FIFO of a packet, host
can issue a command (called TX FIFO send command)
to send out the packet stored in the TX FIFO. This func-
tion can be used alternately with the other transmission
that uses TX buffer ring.
All incoming and outgoing packets are stored in these
buffers. Long packet may occupy multiple pages that
are logically contiguous.The descriptor is located at the
beginning of the first page of this multiple-page packet.
Normally there might be some free space left in the last
page of this multiple-page packet which is called frag-
ment. These fragment will not affect network packet's
data integrity.
P/N:PM0555
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
23
REV. 0.9.8, FEB. 14, 2000