MX25L1006E Datasheet, PDF (17/50 Pages) Macronix International – MX25L1006E

MX25L1006E
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI →
CS# goes high. (see Figure 20)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(10) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) in-
struction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any ad-
dress of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly
at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected
and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code→ 3-byte address on SI →
CS# goes high. (see Figure 21)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
(11) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte
boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-
ecuted.
The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. (see
Figure 22)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip
is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when
BP1, BP0 all set to "0".
(12) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The last address
byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not
all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that
last 8 bit are all 0) of currently selected page. The CS# must keep during the whole Page Program cycle. The CS#
must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruc-
P/N: PM1670
REV. 1.3, NOV. 12, 2013
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