MX25L51245G Datasheet, PDF (15/123 Pages) Macronix International – 3V 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O)

PRELIMINARY
MX25L51245G
8-1. 256Mb Address Protocol
The original 24 bit address protocol of serial Flash can only access density size below 128Mb. For the memory
device of 256Mb and above, the 32bit address is requested for access higher memory size. The MX25L51245G
provides three different methods to access the whole density:
(1) Command entry 4-byte address mode:
Issue Enter 4-Byte mode command to set up the 4BYTE bit in Configuration Register bit. After 4BYTE bit has
been set, the number of address cycle become 32-bit.
(2) Extended Address Register (EAR):
configure the memory device into four 128Mb segments to select which one is active through the EAR<0-1>.
(3) 4-byte Address Command Set:
When issuing 4-byte address command set, 4-byte address (A31-A0) is requested after the instruction code.
Please note that it is not necessary to issue EN4B command before issuing any of 4-byte command set.
Enter 4-Byte Address Mode
In 4-byte Address mode, all instructions are 32-bits address clock cycles. By using EN4B and EX4B to enable and
disable the 4-byte address mode.
When 4-byte address mode is enabled, the EAR<0-1> becomes "don't care" for all instructions requiring 4-byte
address. The EAR function will be disabled when 4-byte mode is enabled.
Extended Address Register
The device provides an 8-bit volatile register for extended Address Register: it identifies the extended address (A31~A24)
above 128Mb density by using original 3-byte address.
Extended Address Register (EAR)
Bit 7
A31
Bit 6
A30
Bit 5
A29
Bit 4
A28
Bit 3
A27
Bit 2
A26
Bit 1
A25
Bit 0
A24
For the MX25L51245G the A31 to A26 are Don't Care. During EAR, reading these bits will read as 0. The bit 0 is
default as "0".
P/N: PM2006
REV. 0.01, JAN. 06, 2014
15