MX25L1606EZUI-12G Datasheet, PDF (15/60 Pages) Macronix International – 3V, 16M-BIT [x 1/x 2] CMOS SERIAL FLASH MEMORY

MX25L1606E
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial
Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock
signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is
being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low).
Figure 2. Hold Condition Operation
CS#
SCLK
HOLD#
SI/SIO0
SO/SIO1
(internal)
SO/SIO1
(External)
Valid Data
Don’t care
Valid Data
Don’t care
Valid Data
Bit 7
Bit 6
Bit 5
High_Z
Bit 7
High_Z
Bit 7
Bit 6
Bit 6
Bit 5
CS#
SCLK
HOLD#
SI/SIO0
SO/SIO1
(internal)
SO/SIO1
(External)
Valid Data
Don’t care
Valid Data
Don’t care
Valid Data
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
High_Z
Bit 7
Bit 6
Bit 5
High_Z
Bit 4
Bit 3
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will keep
high impedance until Hold# pin goes high and SCLK goes low. The Serial Data Input (SI) is don't care if both Serial
Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip
Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communica-
tion with chip, the HOLD# must be at high and CS# must be at low.
P/N: PM1548
REV. 1.8, JUN 04, 2015
15