MX29F1610A Datasheet, PDF (14/39 Pages) Macronix International – 16M-BIT [2M x8/1M x16] CMOS SINGLE VOLTAGE FLASH EEPROM

MX29F1610A
RY/BY PIN AND PROGRAM/ERASE
POLLING
RY/BY is a dedicated, open-drain page program and sector
erase completion. It transitions to VOL after a program or
erase command sequence is written to the MX29F1610A,
and returns to VCC when the WSM has finished executing
the internal algorithm. Since RY/BY is an open-drain
output, several RY/BY pins can be tied together in parallel
with a pull-up resistor to VCC.
RY/BY can be connected to the interrupt input of the
system CPU or controller. It is active at all times, not
tristated if the CE or OE inputs are brought to VIH. RY/
BY is also VCC when the device is in erase suspend or
deep power-down modes.
RY/BY pin is not provided in 44-pin SOP package.
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up
and power-down, a write cycle is locked out for VCC less
than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the
command register is disabled and all internal program/
erase circuits are disabled. Under this condition the
device will reset to the read mode. Subsequent writes will
be ignored until the VCC level is greater than VLKO. It is
the user's responsibility to ensure that the control pins are
logically correct to prevent unintentional write when VCC
is above VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE or WE will
not initiate a write cycle.
DATA PROTECTION
The MX29F1610A is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the Read Array mode.
Also, with its control register architecture, alteration of the
memory contents only occurs after successful
completion of specific multi-bus cycle command
sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
P/N: PM0506
REV.1.7, JUN. 15, 2001
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