MX25U8033EBAI-12G Datasheet, PDF (13/72 Pages) Macronix International – DATASHEET

MX25U8033E
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this device, it enters standby mode and remains in the standby mode
until next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it becomes active mode and remains in the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of
SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, RES,
REMS, REMS2, REMS4 and RDSFDP, the shifted-in instruction sequence is followed by a data-out sequence.
After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR,
SE, BE32K, BE, CE, PP, 4PP, RDP, DP, WPSEL, SBLK, SBULK, GBLK, GBULK,ENSO, EXSO, and WRSCUR,
the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. While a Write Status Register, Program or Erase operation is in progress, to the memory array is neglected and
while not affect the current operation of WRSCUR, WPSEL Write Status Register, Program and Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
(Serial mode 0) 0
0
SCLK
shift in
(Serial mode 3) ¹
1
SCLK
SI
MSB
SO
shift out
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1718
REV. 1.7, JUL. 01, 2014
13