MX25L51245GXDI-10G Datasheet, PDF (114/132 Pages) Macronix International – 3V, 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25L51245G
10. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
- 3-byte address mode
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data
could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to
minimum.
Figure 113. RESET Timing
CS#
SCLK
RESET#
tRHSL
tRH tRS
tRLRH
tREADY1 / tREADY2
Table 13. Reset Timing-(Power On)
Symbol Parameter
tRHSL Reset# high before CS# low
tRS Reset# setup time
tRH Reset# hold time
tRLRH Reset# low pulse width
tREADY1 Reset Recovery time
Table 14. Reset Timing-(Other Operation)
Symbol Parameter
tRHSL Reset# high before CS# low
tRS Reset# setup time
tRH Reset# hold time
tRLRH Reset# low pulse width
Reset Recovery time (During instruction decoding)
Reset Recovery time (for read operation)
Reset Recovery time (for program operation)
tREADY2 Reset Recovery time(for SE4KB operation)
Reset Recovery time (for BE64K/BE32KB operation)
Reset Recovery time (for Chip Erase operation)
Reset Recovery time (for WRSR operation)
P/N: PM2006
114
Min.
10
15
15
10
35
Typ.
Max. Unit
us
ns
ns
us
us
Min.
10
15
15
10
40
40
310
12
25
1000
40
Typ.
Max. Unit
us
ns
ns
us
us
us
us
ms
ms
ms
ms
Rev. 1.5, November 21, 2016