MX98726EC Datasheet, PDF (1/56 Pages) Macronix International – SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

MX98726EC
SINGLE CHIP 10/100 FAST ETHERNET
CONTROLLER WITH uP INTERFACE
1.0 Features
• Direct interface to 80188/186 up to 40Mhz.
• Integrated 10/100 TP tranceiver on chip to reduce
overall cost
• Optional MII interface for external tranceiver.
• Fully comply to IEEE 802.3u spec.
• Best fit in network printer and hub/switch manage-
ment application
• A local DMA channel between on-chip FIFOs and
packet memory
• Shared memory architecture allow host and
MX98726EC to use only one single SRAM
• Host DMA can share packet memory with local DMA
with simple hand shake protocol for x188/186 type of
processor
• Supports proprietary local DMA channel to share
packet memory
• Support bus size configuration:
- CPU : 8 bits, SRAM: 8 bits
- CPU : 16 bits, SRAM: 8/16 bits
• Flexible packet buffer partition and addressing space
for 32k, 64k up to 512K bytes
• NWAY autonegotiation function to automatically set
up network speed and protocol
• 3 loop back modes for system level diagnostics
• Rich on-chip register set to support a wide variety of
network management functions
• Support 64 bits hash table for multicast addressing
• Support software EEPROM interface for easy up-
grade of EEPROM content
• Support 1K bits and 4K bits EEPROM interface
• 5V CMOS in 128 PQFP package for minimum board
size application
1.1 Introduction
MX98726EC ( Generic MAC , or GMAC ) is a cost effec-
tive solution as a generic single chip 10/100 Fast Ethernet
controller. It is designed to directly interface 80188, 80186
( host ) without glue logic.Two types of memory sharing
schemes are supported, i.e. interleaved and shared mode
to support a variety of applications. Single chip solution
will help reduce system cost not only on the compo-
nents but also the board size. Full NWAY function with
10/100 tranceiver will ease the field installation, simply
plug the chip in and it will connect itself with the best
protocol available.
The interleaved mode allow uP to access SRAM (
packet/host buffer ) through MX98726EC's local DMA
channel. This way, no extra SRAM interface logic is
needed on the host side. If high performance is desired,
then shared memory mode is another alternative which
allow host to access SRAM on its own by denying SRAM
bus grant to MX98726EC using simple hand shake pro-
tocol. Without SRAM bus grant, MX98726EC will float
its interface connected to the SRAM, therefore host can
utilize its own memory subsystem to conduct its own
SRAM access.
A intelligent built-in SRAM bus arbitor will manage all
the SRAM access requests from host, on-chip transmit
channel and on-chip receive channel. The throughput
of these network channels and MX98726EC's DMA burst
length can be easily adjusted by option bits on the chip.
These options can help system developers to "fine tune"
a best cost/performance ratio.
MX98726EC is also equipped with fast back-to-back
transmit capability which allow software to "fire" as many
transmit packets as needed in a single command. Re-
ceive FIFO also allow back-to-back reception. Optional
EEPROM can be used to stored network network ad-
dress and other information. In case cost is really a con-
cern, most configuration options including network ad-
dress can be programmed through uP.
P/N:PM0729
REV. 1.1, MAY. 28, 2001
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