MX26L6419 Datasheet, PDF (1/45 Pages) Macronix International – 64M [x16] SINGLE 3V PAGE MODE MTP MEMORY

FEATURES
ADVANCED INFORMATION
MX26L6419
64M [x16] SINGLE 3V PAGE MODE MTP MEMORY
• 3.0V to 3.6V operation voltage
• Block Structure
- 64 x 64Kword Erase Blocks
• Fast random / page mode access time
- 100/25 ns Read Access Time (page depth:8-word)
• 128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User Programmable OTP Cells
• 16-Word Write Buffer
- 14 us/word Effective Programming Time
• Enhanced Data Protection Features Absolute Protec-
tion with VPEN = GND
- Flexible Block Locking
- Block Erase/Program Lockout during Power Transi-
tions
Performance
• Low power dissipation
- typical 15mA active current for page mode read
- 80uA/(max.) standby current
• High Performance
- Block erase time: 2s typ.
- Word programming time: 210us typ.
- Block programming time: 0.8s typ. (using Write to
Buffer Command)
• Program/Erase Endurance cycles: 100 cycles
Software Feature
• Support Common Flash Interface (CFI)
- MTP device parameters stored on the device and
provide the host system to access.
Hardware Feature
• ACC pin
- 12V VPP for fast program/erase mode.
• VPEN pin
- For Erase /Program/ Block Lock enable.
• VCCQ Pin
- The output buffer power supply, control the device 's
output voltage.
• RESET pin
- Hardware reset
Packaging
- 48-Lead TSOP
Technology
- Two bits per cell Nbit (0.25u) MTP Technology
GENERAL DESCRIPTION
The MXIC's MX26L6419 series MTP use the most ad-
vance 2 bits/cell Nbit technology, double the storage ca-
pacity of memory cell. The device provide the high den-
sity MTP memory solution with reliable performance and
most cost-effective.
The device organized as by 16 bits of output bus. The
device is packaged in 48-Lead TSOP. It is designed to
be reprogrammed and erased in system or in standard
EPROM programmers.
The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
The device augment EPROM functionality with in-circuit
electrical erasure and programming. The device uses a
command register to manage this functionality.
The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO layer.
The device uses a 3.0V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algo-
rithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0946
REV. 0.3, OCT. 08, 2003
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