MX23C4100 Datasheet, PDF (1/8 Pages) Macronix International – 4M-BIT [512K x 8/256K x 16] MASK ROM

FEATURES
• Switchable organization
- 512K x 8 (byte mode)
- 256K x 16 (word mode)
• Single +5V power supply
• Fast access time:100/120/150ns
• Totally static operation
MX23C4100
4M-BIT [512K x 8/256K x 16] MASK ROM
• Completely TTL compatible
• Operating current: 60mA
• Standby current: 100uA
• Package
- 40 pin DIP (600 mil)
- 40 pin SOP
GENERAL DESCRIPTION
The MX23C4100 is a 5V only, 4M-bit, Read Only
Memory. It is organized as 512Kx8 bits (byte mode) or
as 256Kx16 bit (word mode) depending on BYTE (pin
31) voltage level. MX23C4100 has a static standby
mode, and has an access time of 100/120/150/200ns.
It is designed to be compatible with all microprocessors
and similar applications in which high performance, large
bit storage and simple interfacing are important design
considerations.
PIN CONFIGURATION
40 PDIP/SOP
A17 1
A7 2
A6 3
A5 4
A4 5
A3 6
A2 7
A1 8
A0 9
CE 10
VSS 11
OE 12
Q0 13
Q8 14
Q1 15
Q9 16
Q2 17
Q10 18
Q3 19
Q11 20
40 A8
39 A9
38 A10
37 A11
36 A12
35 A13
34 A14
33 A15
32 A16
31 BYTE
30 VSS
29 Q15/A-1
28 Q7
27 Q14
26 Q6
25 Q13
24 Q5
23 Q12
22 Q4
21 VCC
MX23C4100 offers automatic power-down, with power-
down controlled by the chip enable (CE) input. When
CE is not selected, the device automatically powers
down and remains in a low-power standby mode as long
as CE stays in the unselected mode.
The OE input as well as OE input may be programmed
active Low.
BLOCK DIAGRAM
CE
OE
BYTE
Q15/A-1
CONTROL
LOGIC
OUTPUT
BUFFERS
Q0~Q14
.
.
.
A0~A17
.
ADDRESS
.
INPUTS
.
.
.
VCC
VSS
Y-DECODER
.
.
.
.
.
X-DECODER
.
.
.
Y-DECODER
4M BIT
ROM ARRAY
PIN DESCRIPTION
Symbol
A0~A17
Q0~Q14
CE
OE
BYTE
Q15/A-1
VCC
VSS
Pin Function
Address Input
Data Output
Chip Enable Input
Output Enable Input
Word/Byte Selection
Q15(Word mode)/LSB address(Byte
mode)
Power Supply Pin (+5V)
Ground Pin
P/N:PM0136
REV. 3.8, JUN. 19, 2003
1