MX23C2100 Datasheet, PDF (1/7 Pages) Macronix International – 2M-BIT 256K x 8/128K x 16 CMOS MASK ROM

INDEX
MX23C2100
FEATURES
• Switchable organization
- 256K x 8 (byte mode)
- 128K x 16 (word mode)
• Single +5V power supply
• Fast access time:150/200ns
• Totally static operation
2M-BIT [256K x 8/128K x 16] CMOS MASK ROM
• Completely TTL compatible
• Operating current: 60mA
• Standby current: 100uA
• Package type:
- 40 pin DIP (600 mil)
GENERAL DESCRIPTION
The MX23C2100 is a 5V only, 2M-bit, Read Only
Memory. It is organized as 256K x 8 bits (byte mode) or
as 128K x 16 bit (word mode) depending on BYTE (pin
31) voltage level. MX23C2100 has a static standby
mode, and has an access time of 150/200ns. It is de-
signed to be compatible with all microprocessors and
similar applications in which high performance, large bit
storage and simple interfacing are important design con-
siderations.
PIN CONFIGURATION
40 PDIP
NC 1
A7 2
A6 3
A5 4
A4 5
A3 6
A2 7
A1 8
A0 9
CE/CE 10
VSS 11
OE/OE 12
Q0 13
Q8 14
Q1 15
Q9 16
Q2 17
Q10 18
Q3 19
Q11 20
40 ^A8
39 ^A9
38 ^A10
37 ^A11
36 ^A12
35 ^A13
34 ^A14
33 ^A15
32 ^A16
31 ^BYTE
30 ^VSS
29 ^Q15/A-1
28 ^Q7
27 ^Q14
26 ^Q6
25 ^Q13
24 ^Q5
23 ^Q12
22 ^Q4
21 ^VCC
MX23C2100 offers automatic power-down, with power-
down controlled by the chip enable (CE/CE) input. When
CE/CE is not selected, the device automatically powers
down and remains in a low-power standby mode as long
as CE/CE stays in the unselected mode.
The OE/OE inputs as well as CE/CE input may be pro-
grammed either active High or Low.
BLOCK DIAGRAM
CE/CE
OE/OE
BYTE
Q15/A-1
CONTROL
LOGIC
OUTPUT
BUFFERS
.
.
A0~A16
.
ADDRESS
.
INPUTS
.
.
.
.
VCC
VSS
Y-DECODER
.
.
.
.
.
X-DECODER
.
.
.
Y-DECODER
2M BIT
ROM ARRAY
Q0~Q14
PIN DESCRIPTION
Symbol
A0~A16
Q0~Q14
CE/CE
OE/OE
BYTE
Q15/A-1
VCC
VSS
Pin Function
Address Input
Data Output
Chip Enable Input
Output Enable Input
Word/Byte Selection
Q15 (Word mode)/LSB addr. (Byte
mode)
Power Supply Pin (+5V)
Ground Pin
P/N:PM0134
REV. 2.2, JAN. 28, 1999
1