SCS750 Datasheet, PDF (2/5 Pages) Maxwell Technologies – FLIGHT MODULE

SCS750
Enhanced Features
SuROM/EEPROM
Write enables
FLIGHT/FLIGHT#
FT_RESET#
3.3V
JTAG/PowerPC ICE
UART0 (LVDS/RS422)
3.3V
Inject PPC Errors (3)
CPU Error (3)
Voltage Sense Output
FPGA Silicon Expl.
WD_DISABLE#
Up to 800MHz
>1,800 MIPS
PPC
750FX
DC/DC
Converter
PPC
750FX
Set
Voltage
PPC
750FX
UART0 (LVDS/RS422)
2.5V I/O
Regulator
DC/DC
FPGA
Core
2.5V - PPC
I/O Voltages
1.5V
Power Input: 3.3V / 5V
UART(0/1) - 2 channel (LVDS/RS422)
Actel RT-AXS
SEU Immune FPGA
60X Master
Bus Snooping
Memory Controllers,
Timers (3), Interrupts,
DMA (3), UART's (2)
Watchdog Timer
Mission Timer
PCI
Master
PCI
Target
80 MHz
Oscillator
40MHz Clock
Distribution
SDRAM Interface
Double Device
Correction Reed-
Solomon
EEPROM
Interface
SEC/DED EDAC
System Controller Chip
LOCAL PCI BUS (32 bit, 33MHz)
To FPGA's,
PPC's, SDRAM's
Main Memory
SDRAM
256 MBytes
0.5MB Primary SuROM
0.5MB Secondary SuROM
7.0MB User EEPROM
Power
Switch
EEPROM Write Enable (3)
[J3 Connector]
Local PCI to J4
Actel RT-AXS SEU Immune FPGA
PCI Target
Arbiters 8 channel arbiter
XFMR
XFMR
MIL-STD-
1553
BC/RT/MT
Rad-Hard
(Optional)
1553
Interface
Logic
System
Timers
32 Bit
(4 Timers)
count-
down
GPIO
General
Purpose I/O
Controller
(32 I/O's)
Synch/Asynch
Serial
Communications
Controller (SCC)
(2)
PCI-PCI
Bridge
cPCI Bus, 3.3V
32 bit, 33MHz
33MHz Clock
Distribution
PCI (8)
cPCI (8)
PCI-IF Chip
FP_RESET#
FP_HALT#
RAD Hard
1553 SRAM
3.3V CMOS, 16 Discretes shared with Backplane
66 MHz
Oscillator
LVDS Standard, RS-422 Option [J3 Connector]
3.3V CMOS, 32 Discretes [J3/J5 Connectors]
(3) Timer Synch# Signals (input/output) [J3 Connector]
Auto Controller/Peripheral Configuration
Cold Sparing Capable
Processor & SDRAM Error Logging
Front Panel Test Connector
Front Panel Flight Connector
Single Event Upset Mitigation
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| Doc. # 1004741 | Rev. 7 |
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MICROELECTRONICS SCS750