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98DX4251 Datasheet, PDF (1/2 Pages) –
Marvell Prestera 98DX4251
Next-generation Packet Processor for Service Delivery Applications
PRODUCT OVERVIEW
The Marvell® Prestera® DX family of packet processors enables high-density 10GbE/1GbE solutions in service provider and campus
applications. Prestera 98DX4251 is the eighth-generation Prestera DX product that enables line-rate packet processing with a mix
of 1GbE, 10GbE or Interlaken interfaces. With five levels of carrier class hierarchical QoS enabled via an on-chip traffic manager
coupled with a full complement of virtualization and tunneling capabilities, Prestera 98DX4251 enables a highly differentiated
service delivery paradigm in the access and aggregation layers of next-generation networks.
PCIe2
DDR3
Secure Control
Multi-core ARM® Processor
Network Shield
L2 Multicast
Packet Bu er Memory
Transmit Queues & Shapers
L3 Multicast
Ingress Policers
eRouter
Header
Alteration
Virtual I/F
FlexTunnel®
CarrierSpan®
DCB
Egress Policy
Egress Policers
eBridge
Ingress Policy
Tunneling
& Interfaces
Virtual I/F
FlexTunnel®
CarrierSpan®
DCB
Tra c Manager with HQoS
Network / Interface Ports
OAM
PTP
SyncE
••••••••••
1GbE / 2.5G / 10GbE / 40GbE /ILK
Fig 1. 98DX4251 System Block Diagram
SPECIAL FEATURES
•• eBridging Technology
•• CarrierSpan®
•• Datacenter Bridging
•• On-chip Traffic Manager
BENEFITS
••Highly flexible mechanisms for virtualization of physical resources
- Enable powerful service instantiation, forwarding and monetization
- Suitable for a standard, hybrid or software-defined networking environment
with capabilities beyond OpenFlow 1.3.1
••Full complement of metro Ethernet standards along with the latest service delivery
techniques like viz L2/L3 VPN, Q-in-Q, TR-101, etc.
- Enables business and consumer networking services
••Prioritization and congestion management capabilities for next-generation
datacenter solutions
- Priority flow control and congestion notification enable lossless mode of operation
as well as burst isolation
••Enables carrier class five-level HQoS on chip
- Provides application-level resource allocation and management capabilities
- Enables up to 5 GB of buffering via external memories