88X2222P Datasheet, PDF (1/2 Pages) –

Marvell Alaska X 88X2222P and 88X2242P
Integrated Dual-port and Quad-port Multi-speed Ethernet Transceiver with MACSec,
IEEE 1588 PTP, Electronic Dispersion Compensation Technology and TurboBoost
Backplane Technology
PRODUCT OVERVIEW
The Marvell® 88X2242P transceiver is a fully integrated, single chip solution providing end-to-end data transmission over fiber-
optic networks as well as Twinax copper links which support SFF-8431 requirements. It is a 4-port device that performs all
physical layer functions associated with 10GBASE-R, 2500BASE-X, 1000BASE-X and 10GBASE-W.
The Electronic Dispersion Compensation (EDC) engine exceeds the requirements of IEEE 10GBase-LRM to deliver high-speed
bi-directional point-to-point full duplex data transmission at 10Gbps per port over a legacy multimode fiber. The host side
interface supports 8 ports of 10GBASE-KR, 2500BASE-KX, 1000BASE-KX, 4 ports of RXAUI, or 2 ports of XAUI. The redundant
host interfaces can be multiplexed onto the line interface for applications requiring redundancy.
All host interfaces have TurboBoost KR DSP engine performance that exceeds conventional DFE architectures, enabling 10Gbps
transmission over legacy backplanes.
The device outputs two recovered clocks for use in Synchronous Ethernet applications and supports Precise Timing Protocol
(PTP) Time Stamping based on IEEE1588 v2 and IEEE802.1AS.
The 88X2242P supports the Marvell LinkCrypt® feature, which is based on the IEEE802.1ae MACsec protocol. The 88X2242P
device also supports features required by the IEEE802.1ae MACsec protocol. These include the ability to select and filter
Uncontrolled Port traffic, support of Packet redirection by addition of a new MAC DA, SA and Ethertype, support of latency
minimization for flow control packets, and support for diagnostics, MACsec header retention, and additional statistics counters.
The device also supports the ability to select a Secure Channel by means other than the SCI, FIPS compliance testing, adaptive
rate control to compensate for packet expansion, and Ethertype matching for the uncontrolled path.
PART NUMBER
DESCRIPTION
88X2222P
88X2242P
• 2-PORT WITH MACSec, PTP, EDC and TurboBoost
• 4-PORT WITH MACSec, PTP, EDC and TurboBoost
Quad KR / Quad RXAUI / Dual XAUI
Host Interface
IEEE 1588 PTP + MACsec
Config.
Frame to Reg.
JTAG
MDIO
SynchE
LED
EDC
I2C
SR / LR / DAC / LRM – 10G / 40G
Quad SFP+ / Single QSFP+
Fig 1. 88X2242P System Block Diagram