88X201X Datasheet, PDF (1/2 Pages) –

Marvell Alaska 88X201x
Integrated 10 Gbps 802.3ae Compliant Ethernet Transceivers
PRODUCT OVERVIEW
The Marvell^® Alaska^® X 88X201x series of physical layer (PHY) transceivers is a complete solution for 10GBASE-SR/LR/ER/
SW/LW/EW 802.3ae compliant applications.
The 88X2010, 88X2011, 88X2012, and 88X2013 transceivers are fully integrated single-chip devices that perform all the
physical functions for 10 Gigabit Ethernet (GbE), 10 Gigabit Fibre Channel LAN (88X2010, 88X2012), and LAN/WAN (88X2011,
88X2013) applications, delivering high-speed bi-directional point-to-point data transmissions. The devices provide flexibility
with the 88X2010 and 88X2011 supporting the 10 GbE Attachment Unit Interface (XAUI), and the 88X2012 and 88X2013
supporting the 10 Gigabit Media Independent Interface (XGMII); each adhering to IEEE 802.3ae specifications.
The 88X2012 and 88X2013 include the PMD, PMA, WIS (88X2013 only), and PCS sub-layer standards. The 88X2010 and
88X2011 additionally have an integrated XGXS function for XAUI support (with 88X2011 supporting additional WIS). Each of
these Alaska X 10 GbE PHYs is housed in design-efficient 256-pin 17x17 TFBGA packages.
The Alaska X 88X201x PHYs enable short reach (SR/SW), long reach (LR/LW), or extended reach (ER/EW) applications for
module implementation or system board implementation in LAN or LAN/WAN form. On the system side, the PHYs can support
XAUI or XGMII modes; while on the line-side they support the serial 10 Gbps XFI interface. The XFI interface is ideal for
connecting to the smaller XFP module. In cases of XENPAK, XPAK, or X2 module designs the 88X2011 or 88X2010 can be
integrated onto the module itself.
BLOCK DIAGRAM
Fig 1. Marvell 10 Gbps Ethernet PHYs—88X2010 LAN XAUI/XFI PHY, 88X2011 LAN/WAN XAUI/XFI PHY, 88X2012 LAN XGMII/XFI PHY,
and 88X2013 LAN/WAN XGMII/XFI PHY
KEY FEATURES AND BENEFITS
FEATURES
BENEFITS
• XAUI system-side interface (88X2011/10)
• XGMII system-side interface (88X2012/13)
• Fully integrated limiting amplifier, CMU/CDR, SERDES, PCS/PMA
• Optional WIS for EOS (Ethernet Over SONET) and WAN applications (88X2011/13)
• Integrated XFP reference clock output (divide by 64)
• Exceed SONET jitter requirements
• XG-MDC/MDIO management interface
• Industrial temperature support (88X2011)
• Compatible mode with industry standard interface
• Low pin count, increased PCB trace-ability and lower power
• Enables support for legacy switch and MAC interfaces
• Single-chip solution for 10 GbE applications
• Ability to support LAN only or both LAN/WAN applications with
a single transceiver
• Eliminates requirement for separate XFP reference clock
• Reduce BOM (bill of materials)
• Surpasses stringent SONET jitter requirements
• Flexible management options
• Support for extreme temperature requirements