88W8797 Datasheet, PDF (1/4 Pages) –

series
Marvell Avastar 88W8797 Integrated 2x2
WLAN/Bluetooth/FM Single-Chip SoC
Supports High Throughput Data Rates for Next Generation WLAN Products
PRODUCT OVERVIEW
The Marvell^® Avastar™ 88W8797 is a highly integrated 2x2 wireless local area network (WLAN) System-on-Chip (SoC),
specifically designed to support high throughput data rates for next generation products and is part of the Marvell
Avastar family of wireless devices. The SoC is designed for both simultaneous and independent operation of the
following:
• 2x2 MIMO spatial streams supporting data rates up to MCS15 (300 Mbps)
• IEEE 802.11n/a/g/b payload data rates for Wireless Local Area Network (WLAN)
• Bluetooth 4.0 + HS (supports Low Energy (LE))
• FM transmit and receive (digital encoder/decoder FM radio with RDS/RBDS)
The device supports the 802.11i security standard through implementation of the Advanced Encryption Standard (AES)/
Counter Mode CBC-MAC Protocol (CCMP), Wired Equivalent Privacy (WEP) with Temporal Key Integrity Protocol (TKIP),
Advanced Encryption Standard (AES)/Cipher-Based Message Authentication Code (CMAC), and WLAN Authentication and
Privacy Infrastructure (WAPI) security mechanisms. The device also supports 802.11n Beamformer and Beamformee
functions.
For video, voice, and multimedia applications, 802.11e Quality of Service (QoS) is supported. The device also supports
802.11h Dynamic Frequency Selection (DFS) for detecting radar pulses when operating in the 5 GHz range.
The 88W8797 supports generic interfaces including SDIO 3.0, High-Speed Inter-Chip (HSIC), USB 2.0, high-speed UART,
and PCM for connecting WLAN, Bluetooth, and FM to the host processor. For FM Tx/Rx, the device supports Inter-IC
Sound (I2S) / analog stereo audio interfaces. An I2C-compatible interface is available to connect FM Tx/Rx to the host
processor, as well. FM Tx/Rx can also share the host interface with Bluetooth.
The device is also equipped with a coexistence interface for external, co-located 2.4 GHz radios.
Available packaging includes a TFBGA option.
BLOCK DIAGRAM
JTAG Interface
Power Management
Battery/Low Voltage LDO
Power Down
I2S/PCM
RF Input
RF Output
Sleep Clock
I2S Audio Codec Interface
3-Wire, 4-Wire Interface
2-Wire Serial Interface
1-Wire Serial Interface
SPI Serial EEPROM
GPIO
88W8797
Processor
Feroceon
CPU
ROM
JTAG
CPU
Interface
Timers/
Interrupts
Power
Management
Bluetooth
Bluetooth/BLE
Baseband
FM Tx/Rx
FM RF
Interface/
FM RF
Audio Interface
Audio Codec
Controller
C
LDO
P
U
B
U
S
Encrycption
SRAM
DMA
Peripheral Bus
Clocked
Serial Unit
B
U
GPIO/LED
S
OTP
Peripheral Bus Unit
WLAN MAC/Baseband
802.11 MAC
Rx/TX
2x2 MIMO
802.11
Baseband
(DSSS, OFDM,
2x2 MIMO)
802.11n
Beamform
802.11n
Beamform
I
N
T
E
R
N
A
L
B
U
S
Direct Conversion RF
WLAN RF
2x2 MIMO
LNA
LNA
Bluetooth
RF
Shared
LNA
PA
5 GHz Tx
LNA
5 GHz Rx
PA
2.4 GHz Tx
2.4 GHz Rx
PA _{5 GHz Tx}
LNA
5 GHz Rx
PA _{2.4 GHz Tx}
T/R
Switch
T/R
Switch
T/R
Switch
2.4 GHz/
Bluetooth Rx SP3T
Bluetooth Tx/Rx
Common Analog
Common
Analog Unit
XTAL_IN
XTAL_OUT
Diplexer
(dual-band only)
Diplexer
(dual-band only)
Host Interfaces
SDIO 3.0
Coexistence Interface
(external, co-located 2.4 GHz radio)
SDIO 3.0
HSIC
HSIC
USB 2.0
USB 2.0
High Speed UART
High Speed UART
I2C-Compatible
I2C - compatible (slave)
2.4/5 GHz Tx/Rx
2.4/5 GHz Tx/Rx
Fig 1. Avastar 88W8797 SoC Block Diagram