300 Datasheet, PDF (1/2 Pages) DB Lectro Inc – SCREW TYPE SERIES

300 series
Marvell ARMADA 300/310 SoCs
PRODUCT OVERVIEW
The Marvell^® ARMADA™ 300/310 SoCs are high-performance integrated controllers. The SoCs integrate the Marvell-
developed CPU core which is fully ARMv5TE compliant with a 256KB L2 Cache. The ARMADA 300/310 builds upon
Marvell’s innovative Feroceon^® family of processors, improves performance, and adds new features to reduce bill
of materials (BOM) costs. The ARMADA 300 (88F6282) is suitable for a wide range of applications such as routers,
gateway, media server, storage, thin clients, set-top-box, networking, point of service and printer products. The
ARMADA 310 (88F6283) is a low power version that is targeted for computer peripherals, consumer electronics, add-
on cards, and small form factor devices such as Plug Computers.
The SoCs integrates:
• High-performance single-issue CPU operating at 1.6 GHZ, 1.8 GHz, and 2.0 GHz (88F6282)
• Low-power single-issue CPU operating at 800 MHZ, and 1 GHz (88F6283)
• 16KB-Instruction and 16KB-Data 4-way, set-associative L1 cache
• 256KB unified 4-way, set-associative L2 cache
• 16-bit DDR2/3 memory interface (up to 1066 MHz data rate)
• Two Gigabit Ethernet MACs with interface options
• Audio Video Bridging
• Two PCI-Express ports
• Single USB 2.0 port with integrated PHY
• Two SATA 2.0 ports with integrated PHYs
• LCD controller supporting up to 1080p and UXGA resolutions
• Network security engine with various encryption algorithm support
• Audio and MPEG Transport Stream Interface
• Two TDM Channels, SDIO/MMC, NAND flash, SPI, two TWSI, and two UART interfaces
• DMA/XOR engine with four channels
• RTC and Thermal sensor
• Compact Package (15 x 15mm FCBGA)
The innovative, on-chip crossbar architecture with any-to-any connectivity enables concurrent transactions among
multiple units that results in high system throughput allowing system designers to create high-performance scalable
systems. Tightly integrated CPU and memory controller significantly improves application performance.
BLOCK DIAGRAM
LCD
Controller
Sheeva™ CPU Core
Single Issue
16KB-I, 16KB-D
Up to 2.0GHz
256KB L2
DDR2/3
Controller
2 x GE
MAC
2 x SATA II
with PHY
USB 2.0
with PHY
System Crossbar
2 x PCI-E
2 x TDM
channels
MPEG_TS
Audio
SDIO/MMC
Security
Engine
4 DMA/
XOR
NAND Ctlr
2 x UART
TWSI, SPI
Fig 1. Marvell ARMADA 300/310 SoCs Block Diagram